1. Field of the Invention
The present invention relates to a non-volatile semiconductor storage device, and more particularly to a non-volatile semiconductor storage device of flash memory or the like.
2. Description of the Related Art
Firstly, an example of structure of a conventional flash memory storage device will be described with reference to FIG. 5. A flash memory storage device 20 shown in FIG. 5 is provided with a memory cell array 22 constituted of flash memory. In the memory cell array 22, numerous memory cells 24, which are formed of transistors with floating gates, are arranged in a matrix. The memory cell array 22 is also provided with a plurality of word lines 26. The gate electrodes of the individual memory cells 24 are each connected to one or other of the word lines 26. The word lines 26 are each connected to one of a plurality of address signal lines 30 via a word line driver 28. The memory cell array 22 is further provided with a plurality of source lines 32. The source electrodes of the individual memory cells 24 are each connected to one or other of the plural source lines 32. The memory cell array 22 is yet further provided with a plurality of bit lines 34. The drain electrodes of the individual memory cells 24 are each connected to one or other of the plural bit lines 34.
The plural bit lines 34 are each connected to a bit line selection gate 36. Each bit line selection gate 36 is structured by an N-type transistor 42 and an N-type transistor 48. The bit line 34 is connected to the source electrode of the N-type transistor 42, the gate electrode of the N-type transistor 42 is connected to one of a plurality of positive bit address signal lines 38, and the drain electrode of the N-type transistor 42 is connected to an I/O line 40. At each N-type transistor 48, one of a plurality of negative bit address signal lines 46, which are connected to the respective positive bit address signal lines 38 via inverters 44, is connected to the gate electrode of the N-type transistor 48, the bit line 34 is connected to the drain electrode of the N-type transistor 48, and a reference voltage Vss is supplied to the drain electrode of the N-type transistor 48.
The I/O line 40 is connected to a sense amplifier 50. The sense amplifier 50 is structured with an inverter 52, an N-type transistor 54, an N-type transistor 56, a P-type transistor 58, an inverter 60 and a P-type transistor 62. A sense amplifier activation signal SAEN is inputted to the inverter 52. The sense amplifier activation signal SAEN is inputted to the gate electrode of the N-type transistor 54, the I/O line 40 is connected to the drain electrode of the N-type transistor 54, and the reference voltage Vss is supplied to the source electrode of the N-type transistor 54. The output terminal of the inverter 52 is connected to the gate electrode of the N-type transistor 56, the drain electrode of the N-type transistor 56 is connected to a sense node SN, and the I/O line 40 is connected to the source electrode of the N-type transistor 56. The output terminal of the inverter 52 is connected to the gate electrode of the P-type transistor 58, the drain electrode of the P-type transistor 58 is connected to the sense node SN, and a power supply voltage Vdd is supplied to the source electrode of the P-type transistor 58. The input terminal of the inverter 60 is connected to the sense node SN. The gate electrode and drain electrode of the P-type transistor 62 are connected to the sense node SN, and the power supply voltage Vdd is supplied to the source electrode of the P-type transistor 62.
A data-reading operation for the memory cell array 22 of the flash memory storage device 20 with the structure described above will be described with reference to FIG. 6. At a time t=t0 shown in FIG. 6, the flash memory storage device 20 is in a standby state, and a word line voltage VWL supplied to the word line drivers 28 and potentials WL of each of the word lines 26 are all at the reference voltage Vss. Further, in the standby state, word address signals PX which are propagated by the plural address signal lines 30 and positive bit address signals PY which are propagated by the plural positive bit address signal lines 38 are at the reference voltage Vss. The N-type transistors 42 of each of the bit line selection gates 36 are all off, and the N-type transistors 48 are all on. Thus, potentials BL of the individual bit lines 34 are at the reference voltage Vss. Furthermore, in the standby state, the sense amplifier activation signal SAEN being supplied to the sense amplifier 50 is at the power supply voltage Vdd, the N-type transistor 54 of the sense amplifier 50 is on, and the N-type transistor 56 is off. Thus, a potential IO of the I/O line 40 is at the reference voltage Vss. Further yet, the P-type transistor 58 is on, the potential of the sense node SN is at the power supply voltage Vdd, and a sense amplifier output signal SAOUT is at the reference voltage Vss.
Now, at a data-reading operation commencement time at a time t=t1, the word line voltage VWL supplied to the word line drivers 28 is raised by an unillustrated booster circuit and starts to rise toward a voltage Vrd (Vrd is greater than a threshold Vt of the memory cells 24). Further, at the time t=t1, the signal address signal PX which designates the memory cell 24 that is the object of reading is propagated through the address signal line 30. Thus, the word line 26 that is connected to the reading object memory cell 24 is selected by the word line driver 28. Because the word line voltage VWL is supplied to the selected word line 26, the potential WL of the selected word line 26 also starts to rise toward the voltage Vrd. Furthermore, at the time t=t1, the positive bit address signal PY which designates the reading object memory cell 24 is propagated through the positive bit address signal line 38. Thus, at the bit line selection gate 36 which is connected to the bit line 34 that is connected to the reading object memory cell 24, the N-type transistor 42 turns on and the N-type transistor 48 turns off, and thus the bit line 34 connected to the reading object memory cell 24 is connected to the I/O line 40.
Moreover, at the time t=t1, the sense amplifier activation signal SAEN switches from the power supply voltage Vdd to the reference voltage Vss. As a result, the N-type transistor 54 and P-type transistor 58 of the sense amplifier 50 turn off and the N-type transistor 56 turns on, and the sense node SN is cut off from the supply of the power supply voltage Vdd and connected to the I/O line 40. At this time, the potential of the sense node SN is determined by positive charge accumulated at a capacitance of the sense node SN and negative charge accumulated at a capacitance of the bit line 34 and the I/O line 40. However, the capacitance of the sense node SN is much smaller than the capacitance of the bit line 34 and the I/O line 40, and thus the positive charge accumulated at the capacitance of the sense node SN is discharged, and the potential of the sense node SN falls below a circuit threshold of the sense amplifier 50.
Then, at a time t=t2, because the potential WL of the word line 26 connected to the reading object memory cell 24 is below the threshold Vt of the memory cell 24, the memory cell 24 is not on, regardless of the value of a datum which has been written to the reading object memory cell 24. However, when the potential of the sense node SN falls below the circuit threshold of the sense amplifier 50, the P-type transistor 62 turns on, and the sense node SN, the I/O line 40 and the bit line 34 are charged up by current flowing through the P-type transistor 62. Thus, the potential of the sense node SN, the potential IO of the I/O line 40 and the potential BL of the bit line 34 rise.
Then, at a time t=t3, the potential WL of the word line 26 connected to the reading object memory cell 24 rises above the threshold Vt of the memory cell 24. If a data one has been written to the reading object memory cell 24, the memory cell 24 turns on. In this case, the potential of the sense node SN, the potential IO of the I/O line 40 and the potential BL of the bit line 34 are determined by a ratio of current flowing through the turned-on memory cell 24 to current flowing through the P-type transistor 62. Here, the current flowing through the P-type transistor 62 is smaller than the current flowing through the memory cell 24, and thus the potential of the sense node SN falls, and is below the circuit threshold of the sense amplifier 50. As a result, the power supply voltage Vdd is outputted as the sense amplifier output signal SAOUT from the inverter 60 (i.e., reading data=one).
On the other hand, if a data zero has been written to the reading object memory cell 24, the reading object memory cell 24 stays off. In this case too, the potential of the sense node SN, the potential IO of the I/O line 40 and the potential BL of the bit line 34 are determined by a ratio of current flowing through the turned-off memory cell 24 to current flowing through the P-type transistor 62. Here, the current flowing through the turned-off memory cell 24 is smaller than the current flowing through the P-type transistor 62, and thus the potential of the sense node SN rises, and rises above the circuit threshold of the sense amplifier 50. As a result, the reference voltage Vss is outputted as the sense amplifier output signal SAOUT (reading data) from the inverter 60 (i.e., the reading data=zero).
With regard to the above description, Japanese National publication No. 2005-512268 discloses a technology in which a flash memory has a structure provided with a charge-storing transistor, with a charge-storing gate, and a selection transistor, with a selection gate. When the selection gate is being switched from a first voltage to a second voltage, the charge-storing gate is kept floating by a switching circuit, and the first voltage is set lower than the second voltage.
Recently, flash memories, which are non-volatile memories, have fallen in cost and accordingly have been used in a greater variety of applications. Particularly in regard to flash memories for portable devices, a lowering of operating voltages has been sought with a view to reducing current consumption (power consumption). However, there is a problem with flash memory storage devices with structures as shown in FIG. 5 in that, if operating voltages are lowered, data-reading operations become unstable.
That is, with the flash memory storage device 20 shown in FIG. 5, in order to accurately read data from the memory cell array 22, the circuit must be designed such that, if a current flowing through the P-type transistor 62 is Ip, and a minimum value of a current Ion that flows through the turned-on memory cell 24 is Ionmin and a maximum value of a current Ioff that flows through the turned-off memory cell 24 is Ioffmax, the following condition is always satisfied.Ioffmax<Ip<Ionmin
The currents Ion and Ioff will vary with operating voltage, ambient temperature and the like, but a difference between the current Ion and the current Ioff can be increased by setting an operating voltage (the power supply voltage Vdd) sufficiently high. Accordingly, a sufficient difference between the current Ioffmax and the current Ionmin can be assured, and designing the circuit so as to satisfy the above condition is facilitated.
However, if the operating voltage is lowered, the current Ion is lowered. Moreover, Ion also changes in accordance with a threshold voltage Vtc of the memory cell 24, and when the operating voltage is lowered, a change in the threshold voltage Vtc has a greater effect on the current Ion (that is, a gradient of change of the current Ion with respect to changes in the threshold voltage Vtc is large). Therefore, the current Ion is affected by variations in the threshold voltage Vtc of the individual memory cells 24 which are caused by fabrication variations in the memory cell array 22, and as the operating voltage is lowered, the current Ionmin will have quite a small value. Thus, with a reduction of the operating voltage, the difference between the current Ioffmax and the current Ionmin becomes very small.
In addition, the current Ip which flows through the P-type transistor 62 changes in accordance with a threshold voltage Vtp of the P-type transistor 62, and when the operating voltage is lowered, a change in the threshold voltage Vtp has a greater effect on the current Ip (that is, a gradient of change of the current Ip with respect to changes in the threshold voltage Vtp is large). Therefore, because the current Ip is affected by variations in the threshold voltage Vtp of individual P-type transistors 62 which are caused by fabrication variations of the P-type transistors 62, as the operating voltage is lowered, a range of variation of the current Ip will be large. Thus, when the operating voltage is lowered, it is difficult to design a circuit such that the above-mentioned condition is always satisfied, and data-reading operations become unstable.
In Japanese National Publication No. 2005-512268, structuring a flash memory cell with two transistors (the charge-storing transistor and the selection transistor) is disclosed. However, a technique for realizing an improvement in stability of data-reading operations if the operating voltage is lowered is not mentioned at all.